1. Field of the Invention
The present invention relates to high density phase change memory devices, and particularly to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional 3D array.
2. Description of Related Art
Phase-change-based memory materials, like chalcogenide-based materials and similar materials, can be caused to change phase between an amorphous state and a crystalline state by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher electrical resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistance material to form nonvolatile memory circuits, which can be read and written with random access.
As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers have been looking to techniques for stacking multiple planes of memory cells to achieve greater storage capacity, and to achieve lower costs per bit. Multilayer phase change devices have been proposed in Haring-Bolivar et al., U.S. Patent Application Publication No. US 2008/0101109, published 1 May 2008 (See, FIG. 11a). The Haring-Bolivar et al. structure consists of a number of 2D phase change memory cell arrays, arranged in a stack above one another, in which phase change memory elements arranged directly above one another are actuated and contacted by a selection transistor by way of a common via.
Multilayer processes have been explored for other memory technologies as well. For example, thin film transistor techniques are applied to charge trapping memory technologies in Lai, et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory”, IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node”, IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.
Also, cross-point array techniques have been applied for anti-fuse memory in Johnson et al., “512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory Cells” IEEE J. of Solid-State Circuits, Vol. 38, No. 11, November 2003. In the design described in Johnson et al., multiple layers of word lines and bit lines are provided, with memory elements at the cross-points. The memory elements comprise a p+ polysilicon anode connected to a word line, and an n-polysilicon cathode connected to a bit line, with the anode and cathode separated by anti-fuse material.
In the processes described in Haring-Bolivar et al., Lai, et al., Jung, et al. and Johnson et al., there are several critical lithography steps for each memory layer. Thus, the number of critical lithography steps needed to manufacture the device is multiplied by the number of layers that are implemented. Critical lithography steps are expensive, and so it is desirable to minimize them in manufacturing integrated circuits. So, although the benefits of higher density are achieved using 3D arrays, the higher manufacturing costs limit the use of the technology.
Another structure that provides vertical NAND cells in a charge trapping memory technology is described in Tanaka et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory”, 2007 Symposium on VLSI Technology Digest of Technical Papers; 12-14 Jun. 2007, pages: 14-15. The structure described in Tanaka et al. includes a multi-gate field effect transistor structure having a vertical channel which operates like a NAND gate, using silicon-oxide-nitride-oxide-silicon SONOS charge trapping technology to create a storage site at each gate/vertical channel interface. The memory structure is based on a pillar of semiconductor material arranged as the vertical channel for the multi-gate cell, with a lower select gate adjacent the substrate, an upper select gate on top. A plurality of horizontal control gates is formed using planar electrode layers that intersect with the pillars. The planar electrode layers used for the control gates do not require critical lithography, and thereby save costs. However, critical lithography steps are required at the top and bottom of each of the vertical cells. Also, there is a limit in the number of control gates that can be layered in this way, determined by such factors as the conductivity of the vertical channel, program and erase processes that are used and so on.
It is desirable to provide a structure for three-dimensional integrated circuit memory with a low manufacturing cost, including reliable, very small memory elements.